ASAP: Arizona State Predictive PDK

The ASAP 7nm Predictive PDK was developed at ASU in collaboration with ARM Research.

Register for and download the ASAP7 Calibre Decks.

ASU in conjunction with ARM has developed Calibre Decks for the ASAP7 PDK.

The decks are encrypted.
A design rule manual is included with the distribution.
Also include is a microelectronics journal paper describing the kit.

The ASAP PDK is now available on GitHub for free.

The PDK contains SPICE-compatible FinFET device models (BSIM-CMG), Technology files for Cadence Virtuoso, Design Rule Checker (DRC), Layout vs Schematic Checker (LVS) and Extraction Deck for the 7nm technology node. For more details regarding the technical specifications of the PDK, please refer the PDK documentation and associated publication. Please note that this process design kit is provided as an academic and research aid only and the resulting designs are not manufacturable.

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Current Version

Version 1.7

This version comes with improved cells in the libraries, Full CCS liberty files for the libraries, and improved Calibre xACT3d extraction decks.

News

November 13, 2017 – Release 1p5

Calibre xACT3d extraction is now supported (results may deviate substantially from PEX)
Minor BEOL changes to improve APR
The 7.5 track cell library and Cadence Innovus design collateral (techLEF) are greatly improved
Library is still 4x
GDS2 of cells (but without Vt layers) are provided
.tcl and techLEF support large self-aligned vias for power delivery
HTML datasheets are provided

March 29, 2017 – Release 1p3

A 7.5 track cell library and Cadence Innovus design collateral (techLEF and qrcTechFile) is included
The library supports all 4 threshold voltages and has been tested on designs with over 500k gate cells. cdl, cdl with extracted parasitics, verilog, LEF and Liberty files are supplied, as well as data sheets. We do not include GDS so cell designs can be assigned in course work using the PDK
LEFs and techLEF are sized 4x to work around Innovus academic license limitations on geometries less than 20 nm. Stream in the completed design at 0.25x scaling to run Calibre PEX. The 4x qrcTechFile has been correlated to Caliber PEX with about 1% accuracy (please let us know if you find discrepencies).
BEOL: Minor changes in many layer design rules, especially SADP M4-M7
A small family of memory macro Liberty and LEF files will be released soon!

November 23, 2016 – Release 1p002

BEOL: SADP metal rules finalized, via resistances corrected, some minor tweaks elsewhere.
FEOL: gate leakage accuracy is improved.
These should work with the standard cell libraries. These are beta-testing now.

May 13, 2016 – Downloads from any university are enabled

Release 0p014 (SADP metal rules subject to change–these presently work with fixed pitches but pitch changes may produce incorrect DRCs)

February 20, 2016 – Alpha download enabled. By invitation only

Release 0p013 (via resistances not calibrated)

Contributors

ASU:
Prof. Lawrence T. Clark, Vinay Vashishtha

Manoj Vangala, Ankita Dosi, Lovish Masand, Parshant Rana

Aditya Gujja, Chandarasekaran Ramamurthya

ARM:
Saurabh Sinha, Lucian Shifren, Brian Cline, Greg Yeric

Other students of the EEE598 special topics course that developed the original technology files, example cells, netlisting, DRC and LVS flows:
Alan Sam, Nalim Gupta, Rohit Musalay, Akash Thakare, Srividhya Jambunathan, Ramana Rao Pandeshwar, Jayesh Sohanlal, Chandrakanth Puttaswamygowda, Adesh Namekumar, Varun Kaushik, Sanyogita Singh

Cells:
L. T. Clark, Manoj Vangala, Sai Chaitanya Reddy, Punit Shah, Anant Mithal

Acknowledgements
Mentor Graphics: Tarek Ramadan (for excellent DRC and LVS training at ASU).

Related Publications

L.T. Clark, V. Vashishtha, L. Shifren, A. Gujja, S. Sinha, B. Cline, C. Ramamurthya, and G. Yeric, “ASAP7: A 7-nm FinFET Predictive Process Design Kit,” Microelectronics Journal, vol. 53, pp. 105-115, July 2016. Download_now
V. Vashishtha, L. Masand, A. Dosi and L. T. Clark, “Systematic Analysis of the Timing and Power Impact of Pure Lines and Cuts Routing for Multiple Patterning,” Proc. SPIE DTCO, 2017. SPIE site
V. Vashishtha, L. Masand, A. Dosi, and L. T. Clark, “Design Technology Co-Optimization of Back End of Line Design Rules for a 7 nm Predictive Process Design Kit,” Proc. ISQED, 2017. Download paper
V. Vashishtha, M. Vangala, P. Sharma, and L. T. Clark, “Robust 7-nm SRAM Design on a Predictive PDK,” Proc. ISCAS, 2017. Download paper
L. T. Clark, V. Vashishtha, D. M. Harris, Samuel Dietrich, and Zunyan Wang, “Design Flows and Collateral for the ASAP7 7nm FinFET Predictive Process Design Kit,” Proc. MSE, 2017. Download paper
L. T. Clark and V. Vashishtha, , “Design with sub-10 nm FinFET Technologies,” Presented at CICC, 2017. Download tutorial
V. Vashishtha, M. Vangala, and L. T. Clark, “ASAP7 Predictive Design Kit Development And Cell Design Technology Co-Optimization,” Proc. ICCAD, 2017. Download presentation